Title :
Performance-driven technology mapping for LUT-based FPGAs
Author :
Shin, Hyunchul ; Kim, Chunghee ; Yu, Younguk
Author_Institution :
Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
An effective and iterative optimization technique is developed for technology mapping of lookup table based field programmable gate arrays. In the algorithm, minimal depth of a given optimized Boolean network is found and then the given cost function is minimized by “sweeping” nodes of the given Boolean network without increasing the depth optimization for reconvergent paths and duplication of logic can be automatically considered during the sweeping procedure. Experimental results show that the approach is very promising
Keywords :
Boolean functions; circuit analysis computing; circuit optimisation; delays; field programmable gate arrays; iterative methods; logic CAD; table lookup; LUT-based FPGAs; cost function; iterative optimization technique; logic duplication; lookup table based field programmable gate arrays; minimal depth; optimized Boolean network; reconvergent paths; technology mapping; Automatic logic units; Circuits; Cost function; Field programmable gate arrays; Iterative algorithms; Logic arrays; Programmable logic arrays; Prototypes; Signal processing algorithms; Table lookup;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404580
