A reconfigurable binary/RNS/LNS architecture for DSP

An integrated digital signal processing machine will accept data from a plethera of sensors and/or subsystems which may be running at different speeds and with different precision/dynamic range metrics. Data would be manipulated using a set of algorithms which perform a variety of filtering or transform tasks. The design of such a machine considered in this paper, integrates recent advancements in mesh array synthesis with processor technology. The result is a high-throughput GIPS class DSP machine capable of responding to a wide mix of system and user defined DSP problems.