Title :
Crosstalk noise in future digital CMOS circuits
Author :
Werner, Claudia ; Göttsche, R. ; Worner, A. ; Ramacher, U.
Author_Institution :
Corp. Res, Infineon Technol., Munich, Germany
Abstract :
This paper presents simulation results for crosstalk noise in future CMOS generations down to 35 nm features. The noise voltage is calculated from circuit simulations with lumped RLC networks and static CMOS cells. A static noise margin is derived from inverter characteristics of NAND and NOR gates and a critical wirelength is calculated from considering statistical variations in the chip manufacturing process. The model agrees well with measurements on a quarter micron testchip and predicts a drastic drop of critical wirelengths to 50-60 μm after the 100 nm technology generation
Keywords :
CMOS digital integrated circuits; circuit simulation; crosstalk; integrated circuit measurement; integrated circuit noise; logic simulation; wiring; 35 to 100 nm; 50 to 60 micron; NAND gates; NOR gates; chip manufacturing process; circuit simulations; critical wirelengths; crosstalk noise; digital CMOS circuits; inverter characteristics; lumped RLC networks; noise voltage; simulation results; static CMOS cells; static noise margin; CMOS digital integrated circuits; Circuit noise; Circuit simulation; Crosstalk; Inverters; Manufacturing processes; Predictive models; RLC circuits; Semiconductor device modeling; Voltage;
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0993-2
DOI :
10.1109/DATE.2001.915045
