A quadratic residue processor for complex DSP applications

The performance requirements for high speed real-time Digital Signal Processing (DSP) applications, coupled with the hardware complexity for manipulating data over complex fields can often exceed the capacity of the traditional signal processors. In this paper, a signal processor for complex DSP applications has been developed. It is based on using the Quadratic Residue Number System (QRNS) which establishes parallelism on the functional level and optimizes the required hardware. By employing QRNS, the interaction between the real and imaginary channels in complex arithmetic is eliminated, and two real multiplications are only required to perform complex multiplication. The processor design is optimised for efficient computation of the FFT and signal processing operations based on FFT such as FIR filtering, IFFT, convolution, correlation, and multiplication. This computational versatility is achieved through macroprogrammability. FIFO´s (First-in First-out) are used for storing the input, intermediate, and output data (and coefficients). Customized look-up tables are employed for implementing the residue operations. The developed processor can be employed either as a stand-alone processor or as a peripheral processor (Co-processor).