DocumentCode :
3016856
Title :
In-place delay constrained power optimization using functional symmetries
Author :
Chang, C.-W. ; Bo Hu ; Marek-Sadowska, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
2001
fDate :
13-16 March 2001
Firstpage :
377
Lastpage :
382
Abstract :
In-Place Optimization (IPO) has become the backend methodology of choice to resolve the gap between logic synthesis and physical design as the optimization can be guided by accurate physical information. To perform optimization without perturbing too much the placed netlist, only buffer insertion and gate sizing are commonly used in current design tools. In this paper, we address the problem of delay-constrained power optimization by introducing another degree of freedom: functional symmetry based rewiring. Theoretical results on the effect of using functional symmetry on transition density for power estimation is also derived. Experimental results show that, under the same delay constraint, our technique achieves much better power reduction as compared to the discrete gate sizing only technique.
Keywords :
CMOS logic circuits; circuit CAD; circuit optimisation; delays; integrated circuit design; logic CAD; low-power electronics; buffer insertion; delay constrained power optimization; functional symmetries; functional symmetry based rewiring; gate sizing; in-place optimization; logic synthesis; power estimation; power reduction; transition density; Constraint optimization; Costs; Delay effects; Delay estimation; Design optimization; Energy consumption; Integrated circuit synthesis; Logic design; Mobile computing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich, Germany
ISSN :
1530-1591
Print_ISBN :
0-7695-0993-2
Type :
conf
DOI :
10.1109/DATE.2001.915052
Filename :
915052
Link To Document :
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