T2: Statistical Methods for VLSI Test and Burn-in Optimization

VLSI circuits have been traditionally tested individually following manufacture; the same tests being applied to all ICs. However, as manufacturing test costs continue to show a disproportionate increase in relation to IC fabrication costs, innovative new statistical methods are being introduced to optimize testing. Such methods fall into two broad categories: those that exploit statistical information in regard to the variation of process parameters on wafers, and those that exploit the statistics of defect distributions on wafers. This tutorial presents test methodologies that span both these categories and illustrate their effectiveness with experimental results from a number of recent studies on production circuits from LSI Logic, IBM, Intel and TI