DFT Aware Layout - Layout Aware DFT

The era of the SOC and sub 100nm process technologies has created several new sets of challenges for the test engineer. One of these is the return to prominence of the effect of test infrastructure on the overall physical design of the device. This time it is not impact of logic overhead which is at the top of the list but the need for DFT to interact with the design implementation process at multiple critical points. Whether it is the floorplanning of MBIST controllers, the placement of MISR structures for test signature capture, the extraction of detailed timing for delay testing, the identification of candidates for bridge fault testing, even the use of testing diagnostics in the development of an effective DFM/DFY strategy, the interactions between test engineering and layout engineering are demanding new levels of integration. This talk will identify some of these areas, discuss ways in which they can be addressed, and a few of the consequences if they aren’t.