Architecture and implementation of a VLIW supercomputer

Author

Colwell, Robert P. ; Hall, W. Eric ; Joshi, Chandra S. ; Papworth, David B. ; Rodman, Paul K. ; Tornes, J.E.

Author_Institution

Multiflow Comput. Inc., Branford, CT, USA

fYear

1990

fDate

12-16 Nov 1990

Firstpage

910

Lastpage

919

Abstract

Very-long-instruction-word (VLIW) computers achieve high performance by exploiting the fine-grain parallelism present in sequential or vectorizable code. Multiflow´s /200 and /300 VLIW systems yielded near-supercomputer performance by this means despite the relatively slow (65 ns) clocks. With its much faster clock period (15 ns) and architectural improvements, the new /500 system attains approximately 4-9× the performance of its predecessors. The authors describe the /500 architecture and implementation (i.e. TRACE/500), with special attention paid to the tradeoffs involved in designing very-high-speed VLIWs

Keywords

computer architecture; pipeline processing; 100k ECL; 128 bit; 15 ns clock period; 32 bit; 64 bit; 66.7 MHz; TRACE/500; VLIW architecture Multiflow, very long instruction word computer; VLIW supercomputer; fine-grain parallelism; vectorizable code; Business; Clocks; Computer architecture; Concurrent computing; Hardware; High performance computing; Operating systems; Parallel processing; Supercomputers; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Supercomputing '90., Proceedings of

Conference_Location

New York, NY

Print_ISBN

0-8186-2056-0

Type

conf

DOI

10.1109/SUPERC.1990.130118

Filename

130118