Towards an efficient implementation of sequential Montgomery Multiplication

A method to generate efficient implementations of sequential Montgomery Multiplication (MM) is proposed. It is applied to radix-2 MM, but could be used for other radices. An efficient solution is obtained when inactive adders in a cycle are re-assigned to perform useful computation. The resulting hardware algorithm and architecture accelerate the modular multiplication by looking ahead the input data of two iterations and in some cases compressing two iterations in one, without increasing the iteration time too much. Experiments show 33.6% average reduction in clock cycles when proposed multiplier is applied to implement modular exponentiation in the 2048-bit RSA cryptosystem.