Fast parasitic-aware synthesis methodology for high-performance analog circuits

In this paper a fast parasitic-aware synthesis approach of CMOS analog circuit is presented. Instead of the conventional approach of circuit sizing followed by layout generation, extraction and verification, we propose a method that considers the performance constraints and layout induced parasitics simultaneously within a concurrent phase of circuit synthesis. The proposed methodology is tested with high-performance analog circuits in different technologies and the experimental results demonstrate the high efficacy of this synthesis approach.