DocumentCode :
3017395
Title :
High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm
Author :
Monga, Sushrant
Author_Institution :
STMicroelectron., Noida, India
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
2171
Lastpage :
2174
Abstract :
An architecture for the scalable speed and multiple supply voltage range of 1.6 V to 3.6 V, low voltage to high voltage level shifter has been proposed. The buffer containing the level shifter is fabricated in 40 nm CMOS process by thin oxide (32 Å thick) devices whose stress limit is 1.98 V (max). The technique generates a set of dynamic differential bias signals as a function of input data sequence, output state of the level shifter and the supply voltage for a given process and temperature to ensure the reliable operation of the level shift stage. The measurement results confirmed successful operation at 40 Mbps with 10 pF load on IO pad, with multiple supplies, 1.8 V - 2.7 V - 3.6 V.
Keywords :
CMOS integrated circuits; buffer circuits; integrated circuit measurement; integrated circuit reliability; CMOS process; bit rate 40 Mbit/s; buffer circuit; capacitance 10 pF; dynamic differential bias signal; high speed stress tolerant; high voltage CMOS level shifter architecture; input data sequence function; low voltage CMOS level shifter architecture; multiple supply voltage; operation reliability; size 40 nm; stress limit; thin oxide device; voltage 1.6 V to 3.6 V; CMOS integrated circuits; CMOS technology; Generators; Logic gates; Low voltage; Stress; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271719
Filename :
6271719
Link To Document :
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