DocumentCode
3017539
Title
Implementation of a linear histogram BIST for ADCs
Author
Azais, F. ; Bernard, S. ; Bertrand, Y. ; Renovell, M.
Author_Institution
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear
2001
fDate
2001
Firstpage
590
Lastpage
595
Abstract
This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time
Keywords
analogue-digital conversion; built-in self test; integrated circuit testing; ADCs; linear histogram BIST; operating mode; test time; time decomposition technique; Automatic testing; Built-in self-test; Circuit testing; Digital signal processing; Hardware; Histograms; Linearity; Manufacturing industries; Monitoring; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location
Munich
ISSN
1530-1591
Print_ISBN
0-7695-0993-2
Type
conf
DOI
10.1109/DATE.2001.915083
Filename
915083
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