FAR-DS: full-plane AWE routing with driver sizing

Author

Hu, Jiang ; Sapatnekar, Sachin S.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1999

fDate

1999

Firstpage

84

Lastpage

89

Abstract

We propose a Full-plane AWE Routing with Driver Sizing (FAR-DS) algorithm for performance driven routing in deep sub-micron technology. We employ a fourth order AWE delay model in the full plane, including both Hanan and non-Hanan points. Optimizing the driver size simultaneously extends our work into a two-dimensional space, enabling us to achieve the desired balance between wire and driver cost reduction, while satisfying the timing constraints. Compared to SERT experimental results showed that our algorithm can provide an average reduction of 23% in the wire cost and 50% in the driver cost under stringent timing constraints

Keywords

circuit layout CAD; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; multichip modules; network routing; timing; waveform analysis; 0.18 mum; FAR-DS algorithm; Hanan points; IC technology; MCM technology; asymptotic waveform evaluation; buffer sizing; deep sub-micron technology; driver cost reduction; driver size optimization; driver sizing; fourth order AWE delay model; full-plane AWE routing; interconnect performance; nonHanan points; performance driven routing; timing constraints; two-dimensional space; wire cost reduction; Computer errors; Contracts; Costs; Delay; Routing; SPICE; Space technology; Timing; Topology; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.781275

Filename

781275