Title :
Simultaneous routing and buffer insertion with restrictions on buffer locations
Author :
Zhou, Hai ; Wong, D.F. ; Liu, I-Min ; Aziz, Adnan
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay
Keywords :
VLSI; circuit layout CAD; delays; integrated circuit interconnections; integrated circuit layout; network routing; 0.18 mum; RC models; VLSI; block placement; buffer insertion; buffer location restrictions; fast path algorithm; global interconnect routing; macro blocks; maze routing; minimum Elmore delay; polynomial time exact algorithm; sink pin; source pin; Delay effects; Fabrication; Intellectual property; Minimization methods; Permission; Pins; Polynomials; Routing; Very large scale integration; Wires;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781279
