Using an FPGA to accelerate pupil isolation in iris recognition

Author

Shafer, Jennifer L. ; Ngo, Hau ; Ives, Robert W.

Author_Institution

Dept. of Electr. & Comput. Eng., United States Naval Acad., Annapolis, MD, USA

fYear

2010

fDate

7-10 Nov. 2010

Firstpage

1774

Lastpage

1777

Abstract

Iris recognition is an important application in the Department of Defense and the Department of Homeland Security. An algorithm that is both accurate and fast in a hardware design that is small and transportable are crucial to the implementation of this tool. As part of an ongoing effort to meet these criteria, this paper improves a segment of the US Naval Academy´s RED iris recognition algorithm, namely pupil isolation. We show a significant speed-up of pupil isolation by implementing this portion of the algorithm on a Field Programmable Gate Array (FPGA).

Keywords

field programmable gate arrays; iris recognition; Department of Defense and the Department of Homeland Security; FPGA; US Naval Academy RED iris recognition algorithm; field programmable gate array; hardware design; pupil isolation; Algorithm design and analysis; Clocks; Field programmable gate arrays; Image edge detection; Iris recognition; Pixel; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-9722-5

Type

conf

DOI

10.1109/ACSSC.2010.5757846

Filename

5757846