DocumentCode :
3017902
Title :
CPU for PlayStation(R)2
Author :
Tago, Haruyuki ; Hashimoto, Kazuhiro ; Ikumi, Nobuyuki ; Nagamatsu, Masato ; Suzuoki, Masakazu ; Yamamoto, Yasuyuki
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fYear :
2001
fDate :
2001
Firstpage :
696
Abstract :
Processors designed for computer entertainment must perform 3D graphics calculations, especially geometry and perspective transformations. In the PlayStation(R)2, we introduced the new idea of synthesizing emotion called Emotion Synthesis and devised a new processor architecture to support its graphics demands. The architecture is embodied in the PlayStation(R)2´s “Emotion Engine” CPU, which uses vector units (VUs) as the key units for floating-point calculations. Emotion synthesis means the real-time synthesis of a computer graphics animation scene that projects a great deal of atmosphere. For example, when a female character walks into a video game scene, her motion must be determined by solving physical equations in response to interactive events instead of replaying prerecorded data. Moreover, differential equations with a large number of variables must be used to describe, for example, the waving motions of her hair in a breeze. For authenticity in emotion synthesis, the CPU must execute these calculations in real time. “Emotion Engine” (“EE”) is a system LSI including a 300 MHz 128-bit 2-way superscalar RISC core, two Vector Units (“VU”s), Image Processing Unit (“IPU”) for MPEG-2 stream decode, a 10-channel memory access (DMA) controller, two channel Rambus(R) memory controller (RAC) and other peripheral modules. 13.5 M transistors are integrated on 15.02 mm×15.04 mm die with 0.25 μm device technology with 0.18 μm gate length. Design strategy and LSI design methodologies and CAD for “Emotion Engine” LSI are presented with emphasis on practical aspects of verification and timing closure. A combination of simulation, emulation and formal verification ensured the functional first silicon for system evaluation. In order to control wire delay in early design stage, floor-plan based synthesis and wire load estimation are adopted for quick timing closure
Keywords :
computer animation; computer games; floating point arithmetic; microprocessor chips; real-time systems; reduced instruction set computing; 0.18 micron; 0.25 micron; 128 bit; 300 MHz; 3D graphics calculations; Emotion Engine; Emotion Synthesis; LSI design methodologies; MPEG-2 stream decode; PlayStation2; animation scene; computer entertainment; differential equations; floating-point calculations; floor-plan based synthesis; formal verification; geometry; perspective transformations; physical equations; processor architecture; real time; superscalar RISC core; system LSI; timing closure; vector units; wire load estimation; Central Processing Unit; Computer graphics; Control system synthesis; Delay estimation; Large scale integration; Layout; Process design; Random access memory; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
ISSN :
1530-1591
Print_ISBN :
0-7695-0993-2
Type :
conf
DOI :
10.1109/DATE.2001.915101
Filename :
915101
Link To Document :
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