An Effective Design for Hierarchical Test Generation Based on Strong Testability

Author

Ichihara, Hideyuki ; Okamoto, Naoki ; Inoue, Tomoo ; Hosokawa, Toshinori ; Fujiwara, Hideo

Author_Institution

Graduate Sch. of Inf. Sci., Hiroshima City Univ.

fYear

2005

fDate

21-21 Dec. 2005

Firstpage

288

Lastpage

293

Abstract

Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths

Keywords

VLSI; automatic test pattern generation; design for testability; integrated circuit testing; VLSI circuits; datapath delay penalty; hardware overhead; heuristic algorithm; hierarchical test generation; test plan generation algorithm; testability; Circuit testing; Design for testability; Educational institutions; Hardware; Heuristic algorithms; Logic circuits; Logic design; Logic testing; Time sharing computer systems; Very large scale integration; Hierarchical test generation; datapath; strong testability; test plan.;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2005. Proceedings. 14th Asian

Conference_Location

Calcutta

ISSN

1081-7735

Print_ISBN

0-7695-2481-8

Type

conf

DOI

10.1109/ATS.2005.23

Filename

1575444