A cascadable adaptive FIR filter VLSI IC

This paper describes the architecture and features of the Motorola DSP56200, an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with FIR and adaptive FIR digital filtering applications. The DSP56200 is implemented in high performance, low power 1.5µm HCMOS technology and is available in a 28 pin DIP package. The on-chip computation unit includes a 97.5 ns 24×16-bit multiplier with a 40-bit accumulator, a 256×24-bit coefficient RAM, and a 256×16-bit data RAM. Three modes of operation allow the part to be used as a single FIR filter, a dual FIR filter, or a single adaptive FIR filter, with up to 256 taps/chip. In the adaptive FIR filter mode, the part performs the FIR filtering and LMS coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19 kHz sampling rate, 256 tap adaptive FIR filter. Programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceller configuration will be presented. Typical applications of the part will also be described.