A SAT-based diagnosis pattern generation method for timing faults in scan chains

Scan is a widely used DFT technique to improve test and diagnosis quality. However, failures on scan chain itself account for up to 30% of chip failures. In this paper, a SAT-based technique is proposed to generate patterns to diagnose four types of timing faults in scan chains. The proposed method can efficiently generate high quality diagnostic patterns while achieving high diagnosis resolution. Further more, the computation overhead of equivalent faults proving is reduced. Experimental results on ISCAS´89 benchmark circuits show that the proposed method can reduce at least 70% diagnostic patterns´ volume and 60% CPU time compared with other works.