Low-power delay test architecture for pre-bond test

Three-dimensional integrated circuits (3D-ICs) create new test challenges. Because of the limited number of test pads available in pre-bond test, the IR-drop can become a serious problem in delay test. In this paper we present a low-power delay test architecture, in which scan flip-flops are partitioned into groups that can be selected turned off in the capture cycles. As a result, power consumption in the capture cycles can be reduced significantly and thus IR-drop can be alleviated. Experimental results show that the proposed method can achieve the same level of delay fault coverage with roughly the same number of test vectors, while capture cycle power consumption is lower.