• DocumentCode
    3018419
  • Title

    Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability

  • Author

    Ghosh, S. ; Bhunia, S. ; Roy, K.

  • Author_Institution
    Purdue University, IN
  • fYear
    2005
  • fDate
    18-21 Dec. 2005
  • Firstpage
    404
  • Lastpage
    409
  • Abstract
    Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confidence. In this paper, we analyze the testability in a new style of logic design based on Shannon’s decomposition and supply gating. We observe that tree structure of a logic circuit due to Shannon’s decomposition makes it intrinsically more testable than conventionally synthesized circuit, while at the same time entailing an improvement in active power. We have analyzed three different aspects of testability of a circuit: a) IDDQ test sensitivity b) test power during scan-based testing, and c) test length (for both ATPG-generated deterministic and random patterns). Simulation results on a set of MCNC benchmarks show promising results on all the above aspects. We have also demonstrated that the new logic structure can improve parametric yield of a circuit under process variations when considering a bound on circuit leakage.
  • Keywords
    Benchmark testing; Circuit simulation; Circuit synthesis; Circuit testing; Costs; Logic circuits; Logic design; Logic testing; Pattern analysis; Tree data structures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.98
  • Filename
    1575463