Title :
An O-tree representation of non-slicing floorplan and its applications
Author :
Guo, Pei-Ning ; Cheng, Chung-Kuan ; Yoshimura, Takeshi
Author_Institution :
Mentor Graphics Corp., San Jose, CA, USA
Abstract :
We present an ordered tree, O-tree, structure to represent non-slicing floorplans. The O-tree uses only n(2+[Ig n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n! 22n-2/n1.5). This is very concise compared to a sequence pair representation which has O((n!)2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n2 (n/4e)n). The complexity of the O-tree is even smaller than a binary tree structure for slicing floorplan which has O(n! 25n-3/n1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC benchmarks show promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method
Keywords :
circuit complexity; circuit layout CAD; integrated circuit layout; trees (mathematics); O-tree representation; compacted placement; constraint graph; deterministic floorplanning algorithm; nonslicing floorplan; ordered-tree structure; rectangular blocks; Binary trees; Circuits; Clustering algorithms; Graphics; National electric code; Permission; Process design; Tree data structures; Tree graphs; Wire;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781324