A Unified Approach to Partial Scan Design using Genetic Algorithm

In the present day, most of the designs for testability (DFT) strategies are based on full and partial scan designs. Different methods are used to select the flip-flops for the scan path, which are based on the structure of the circuit, and some testability measures. However, most of the methods just focus on a single method and at most two for partial scan path design. In this paper, we propose a new approach for selection of flip-flops in partial scan path design. We try to incorporate three different methods into one and optimize them using genetic algorithm. The testability approach is used to estimate how the selection of a particular flip-flop affects its neighboring flip-flops. Focus is also given to those flip-flops whose selection tends to break maximum number of cycles. Finally we try to optimize is to minimize the overall power consumption of the modified circuit. The experimental results show that though it is not always possible to improve upon the performances of techniques which focus only on single objective, on an average fairly good results are obtained in terms of fault coverage, number of vectors and the power consumption.