• DocumentCode
    3018462
  • Title

    A Family of Logical Fault Models for Reversible Circuits

  • Author

    Polian, Ilia ; Fiehn, Thomas ; Becker, Bernd ; Hayes, John P.

  • Author_Institution
    Albert-Ludwigs-University, Germany
  • fYear
    2005
  • fDate
    18-21 Dec. 2005
  • Firstpage
    422
  • Lastpage
    427
  • Abstract
    Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
  • Keywords
    ATPG; fault models; quantum circuits; reversible circuits; Circuit faults; Circuit testing; Computational modeling; Computer architecture; Electrical fault detection; Fault detection; Physics computing; Power dissipation; Quantum computing; Quantum mechanics; ATPG; fault models; quantum circuits; reversible circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.9
  • Filename
    1575466