DocumentCode
3018480
Title
Compressing Functional Tests for Microprocessors
Author
Balakrishnan, Kedarnath J. ; Touba, Nur A. ; Patil, Srinivas
Author_Institution
NEC Labs. America, Princeton, NJ
fYear
2005
fDate
18-21 Dec. 2005
Firstpage
428
Lastpage
433
Abstract
In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target unique defects and failure modes. Hence, functional vector compression can help alleviate the cost of functional test. Scan vector compression techniques are generally unsuitable in the functional domain and techniques specially tailored for functional test compression are required. Additionally, it may be possible to perform compression and decompression using software techniques without incurring the overhead of dedicated hardware. This paper proposes a set of software techniques targeted towards functional test compression.
Keywords
Built-in self-test; Circuit testing; Costs; Embedded software; Hardware; Manufacturing; Microprocessors; Phase shifters; Test data compression; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2005. Proceedings. 14th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2481-8
Type
conf
DOI
10.1109/ATS.2005.38
Filename
1575467
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