• DocumentCode
    3018500
  • Title

    Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach

  • Author

    AL-Ars, Zaid ; Vollrath, Jorg ; Hamdioui, Said

  • Author_Institution
    Fac. of EE, Math. & CS, Delft Univ. of Technol.
  • fYear
    2005
  • fDate
    21-21 Dec. 2005
  • Firstpage
    434
  • Lastpage
    439
  • Abstract
    Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modifies the faulty behavior of the memory. This paper introduces an analytical (equation-based) method to give a rough analysis of the faulty behavior of cell opens in the memory, that simplifies the understanding and identifies the major factors responsible for the faulty behavior. Having these factors makes it easier to optimize the circuit and allows extrapolation of the behavior of future technologies. The paper also compares the results of the analytical approach with those from the simulation-based analysis and discusses the advantages and disadvantages of both
  • Keywords
    DRAM chips; fault simulation; integrated circuit testing; defect simulation; electrical simulation; faulty DRAM behavior; memory chips; memory testing; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Computer aided manufacturing; Equations; Fabrication; Fault diagnosis; Predictive models; Random access memory; DRAMs; analytical evaluation; defect simulation; faulty behavior; memory testing.;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • Conference_Location
    Calcutta
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.71
  • Filename
    1575468