• DocumentCode
    3018564
  • Title

    Managing Test and Repair of Embedded Memory Subsystem in SoC

  • Author

    Chandramouli, R.

  • Author_Institution
    Virage Logic, Fremont, CA
  • fYear
    2005
  • fDate
    21-21 Dec. 2005
  • Firstpage
    452
  • Lastpage
    452
  • Abstract
    This presentation discusses one such IIP targeted towards the test and repair of embedded memories. An advanced technique called the STARtrade (self test and repair) memory system embedded on-chip diagnoses failed memory bits and repairs the failed memory in real time using the redundant resources (row or columns or both) in the memory. The STAR processor itself has four key test and repair functions. They are BIST (built-in-self-test) to create memory specific test patterns, a BIST diagnostics to analyze and identify the failure, BIRA (built-in redundancy analysis), and the repair and redundancy allocation logic with algorithms to reconfigure the memory rows and columns to be topologically efficient post repair
  • Keywords
    built-in self test; embedded systems; integrated circuit testing; integrated memory circuits; logic testing; system-on-chip; STAR memory system; STAR processor; allocation logic; built-in redundancy analysis; built-in-self-test; embedded memory subsystem; failed memory bits; infrastructure IP; self test and repair; system-on-chip; test patterns; Algorithm design and analysis; Automatic testing; Built-in self-test; Failure analysis; Logic testing; Memory management; Pattern analysis; Real time systems; System testing; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • Conference_Location
    Calcutta
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.79
  • Filename
    1575473