Computer-aided design-verification vector generation

Author

Stroud, Charles E. ; Ericson, M. Nance

Author_Institution

Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

144

Lastpage

147

Abstract

This paper describes the features and usage of a CAD tool that assists ASIC designers in the generation of design-verification vectors. The designer describes the ASIC interfaces as well as the desired operations to be performed in an assembly language format from which the CAD tool generates the actual input stimulus and timing relationships for the design-verification simulation

Keywords

application specific integrated circuits; assembly language; circuit CAD; integrated circuit design; ASIC design; ASIC interfaces; CAD tool; assembly language format; computer-aided design verification; design-verification simulation; vector generation; Application specific integrated circuits; Assembly; Circuit simulation; Clocks; Design automation; Laboratories; Legged locomotion; Logic; Signal design; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404590

Filename

404590

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3018569