Title :
A register-transfer-level fault simulator for permanent and transient faults in embedded processors
Author :
Rousselle, C. ; Pflanz, M. ; Behling, A. ; Mohaupt, T. ; Vierhaus, H.T.
Author_Institution :
Kisters AG, Germany
Abstract :
HEARTLESS (Hierarchical Register-Transfer-Level Fault-Simulator for Permanent & Transient Faults) was developed to simulate the behavior of complex sequential designs like processor cores in case of transient and permanent faults. HEARTLESS can be enhanced by propagation over macros described in a C++ function. Available is a C-interface for access to internal signals during the simulation
Keywords :
C++ language; fault simulation; hardware description languages; logic CAD; sequential circuits; C++; HEARTLESS; embedded processors; permanent and transient faults; processor cores; register-transfer-level fault simulator; sequential design; transient faults; Automatic testing; Circuit faults; Circuit simulation; Clocks; Delay; Libraries; Monitoring; Process design; Runtime; Signal analysis;
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0993-2
DOI :
10.1109/DATE.2001.915148
