Title :
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Author :
Wei, Liqiong ; Chen, Zhaiipiiig ; Roy, Kaushik ; Ye, Yibin ; De, Vivek
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-Vth (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique
Keywords :
CMOS logic circuits; logic CAD; low-power electronics; timing; adder; back-tracing algorithm; design methodology; high threshold transistors; leakage reduction; low power applications; mixed-threshold-voltage CMOS circuit; performance constraints; priority selection algorithm; static timing analysis; transistor delay slack; transistor-level threshold assignment; Application software; CMOS logic circuits; CMOS process; CMOS technology; Circuit synthesis; Leakage current; Low voltage; MOSFETs; Permission; Threshold voltage;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781355
