DocumentCode
3019058
Title
Efficient finite field digit-serial multiplier architecture for cryptography applications
Author
Bertoni, Guido ; Breveglieri, Luca ; Fragneto, Pasqualina
Author_Institution
Politecnico di Milano, Italy
fYear
2001
fDate
2001
Firstpage
812
Abstract
Cryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated
Keywords
VLSI; computer architecture; cryptography; embedded systems; logic design; multiplying circuits; optimisation; smart cards; GBB algorithm; VLSI multiplier architecture; cryptography; efficient elliptic code; embedded systems; finite field digit-serial multiplier architecture; finite field multiplication; power consumption; recoding; smart-cards; time latency; Algorithm design and analysis; Clocks; Computer architecture; Delay; Design optimization; Elliptic curve cryptography; Embedded system; Galois fields; Polynomials; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location
Munich
ISSN
1530-1591
Print_ISBN
0-7695-0993-2
Type
conf
DOI
10.1109/DATE.2001.915150
Filename
915150
Link To Document