A practical gate resizing technique considering glitch reduction for low power design

Author

Hashimoto, Masanori ; Onodera, Hidetoshi ; Tamaru, Keikichi

Author_Institution

Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan

fYear

1999

fDate

1999

Firstpage

446

Lastpage

451

Abstract

We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. The effect of our method is verified experimentally using 8 benchmark circuits with a 0.6 μm standard cell library. Our method reduces the power dissipation from the minimum-sized circuits further by 9.8% on average and 23.0% maximum. We also verify that our method is effective under manufacturing variation

Keywords

CMOS logic circuits; circuit optimisation; combinational circuits; integrated circuit design; logic design; low-power electronics; 0.6 mum; CMOS combinational circuits; benchmark circuits; capacitive power consumption; gate resizing technique; glitch reduction; glitch transitions; low power design; manufacturing variation; minimum-sized circuits; partial-swing transitions; power dissipation; power optimization; short-circuit power consumption; skew fluctuation; standard cell library; statistical estimation; synchronous design style; Circuits; Delay; Design optimization; Energy consumption; Fluctuations; Manufacturing; Optimization methods; Permission; Power dissipation; Power engineering computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.781358

Filename

781358