A novel efficient FPGA architecture for HMMER acceleration

In this paper, a novel efficient FPGA-based architecture for the acceleration of the hmmsearch tool for biological sequence-to-profile alignment, which is based on the Viterbi algorithm, is presented. Typical hardware implementations of this Dynamic Programming-based algorithm require an amount of block RAMs proportional to the profile length in order to hold emission and transition probability scores for alignment matrix computation. In contrast, the proposed architecture uses the abundant logic slices available on FPGA as look-up tables or configuration elements (CEs) to hold the probability scores. Moreover, double buffering is used to efficiently manage a fixed number of CEs (equal to two i.e. CE₀ and CE₁) by scheduling both alignment matrix computation and processing element (PE) configuration to run simultaneously. This way, both time and space complexities are optimized, thus supporting multiple-pass or folded computation with significant throughput increases. In addition, with the fixed number of CEs, computational parameters such as number of folds and query profile´s length could be changed at run time. Implementation results show that the core achieves 5.86 normalized speed-up per logic cell/process technology compared to the state-off-the-art.