Title :
Buffer insertion with accurate gate and interconnect delay computation
Author :
Alpert, Charles J. ; Devgan, Anirudh ; Quay, Stephen T.
Author_Institution :
IBM Austin Res. Lab., TX, USA
Abstract :
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these methods use simplified interconnect and gate delay models. These models may lead to inferior solutions since the optimized objective is only an approximation for the actual delay. We propose to integrate accurate wire and gate delay models into Van Ginneken´s buffer insertion algorithm (1990) via the propagation of moments and driving point admittances up the routing tree. We have verified the effectiveness of our approach on an industry design
Keywords :
application specific integrated circuits; circuit layout CAD; circuit optimisation; delay estimation; integrated circuit interconnections; integrated circuit layout; network routing; timing; ASIC; Van Ginneken buffer insertion algorithm; buffer insertion; deep submicron design; driving point admittances; gate delay computation; interconnect delay computation; moment propagation; routing tree; timing optimization; Algorithm design and analysis; Capacitance; Delay effects; Iterative algorithms; Laboratories; Permission; Propagation delay; Routing; Timing; Wire;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781363
