An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding

Flexible baseband receivers gain the interest of many research efforts to enable the design of future multi-modes multistandards terminals. A main challenge in this domain is to provide this flexibility with minimum overhead in terms of area, speed, and energy. In this regard, heterogeneous multiprocessor platforms are emerging as a promising implementation solution. However, the heterogeneity of such platforms makes it complex to find the required number of processors supporting a specific configuration (i.e. requirements level). This paper investigates, in this context, the significant optimization potential both at design-time and at run-time regarding the selection of the most appropriate hardware configuration of a multiprocessor platform for iterative demapping and channel decoding. A formal representation of the architectural solution space which allows designers to find the minimum hardware configuration is proposed. The proposed approach is illustrated through a flexible multi-ASIP hardware platform for iterative demapping and channel decoding.