Optimal buffered clock tree synthesis

Given a topology and a library of buffers, we propose a clock buffer synthesis using a dynamic programming algorithm which finds optimum buffer sizes and insertion levels. At the same time, we optimize wire widths which further reduces propagation delay and the sensitivity of clock skew. Careful fine tuning by shifting buffer locations at the last stage preserves the zero skew property and reduces the wire length. Extensive experiments show a significant delay reduction compared to the best known clock topology generation algorithm. We also show a significant reduction of skew sensitivity under manufacturing variations