An automated test framework for experimenting with stochastic behavior in reconfigurable logic

In this paper, we present an automated test framework for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate-level. As an experimental platform, we propose to use an FPGA due to the proven value of reconfigurable architectures in design space exploration. We hypothesize that stochastic behavior can be introduced in FPGAs using external noise sources; a fact that is later confirmed by characterizing the behavior of an FPGA IO block subject to voltage/frequency scaling and V_dd-noise. The framework provides easy interfacing with laboratory equipment, design of experiment capabilities and automatic test execution, thus providing a powerful tool for characterizing stochastic behavior in reconfigurable logic.