SRAM in hold-operation: Modeling the interaction of soft-errors and switching power-supply noise

SRAM failure-rate, induced by failure mechanisms such as process variations or cosmic neutrons, increases with reduction in the supply-voltage. Thus, appropriate supply-voltage margins must be used to mitigate or control the failure-rate. This work models and analyzes the interaction of two failure-mechanisms in an SRAM cell during the hold-operation (standby): (i) power-supply noise (due to switching at clock-edge) and soft-errors (due to radioactivity). Circuit-level simulations are used to analyze this interaction. The effect of random process-variations is accounted for by Monte-Carlo simulations. An error in stored-bit of SRAM cell is a transient phenomenon. Therefore, transient analysis of soft-error is carried out in the presence of power-supply noise and random process-variations by using circuit-level simulations in the UMC CMOS 90nm technology. A stochastic process based supply-voltage is difficult to model; therefore, a lower-envelope of measured supply-voltage from the literature is used as the noisy waveform. The critical-charge, obtained by using injection-current model of Freeman [1], of an SRAM cell is used to calculate the soft-error rate (SER). Simulation results show that the SER depends on the time-average of the noisy supply-voltage and not on its minimum value. The distribution of critical-charge, due to random process-variations, is estimated using simulations.