Experimentally effective clean process to C-V characteristic variation reduction of HKMG MOS devices

In this work, the planar HKMG MOS devices are fabricated on (100) wafer with p-substrate. To improve the samples´ interface roughness between the Si/Ge film and the interface layer, three different clean treatments are considered to fabricate the MOS devices. Among processes, the experiment indicates that HF and water rinse can present hydrogen termination to bond silicon as a good passivation. The measured C-V curves and HRTEM of the fabricated samples show the interface roughness is improved significantly. The extracted shift of flat band voltage (ΔV_fb) and density of interface traps (D_it) have around 50% improvement.