An implementation of a directory protocol for a cache coherent system on FPGAs

As FPGA-based systems evolve towards using networks of heterogeneous processing systems, it is important to develop suitable memory systems. This paper presents a cache coherent system that uses a directory protocol. The Directory component of our system has a pipeline design, where a message, which represents a memory request, is serviced every three cycles. Such a design works well for an FPGA, which is an ideal platform for parallel and streaming-type designs. Our system performs 25% more barriers per second than a previous system by Mirian et al. [1], which uses a snoopy protocol, by making minor changes to the Interconnect and the cache coherence protocol.