A low-power dynamic comparator with time-domain bulk-driven offset cancellation

This paper presents a low-power dynamic comparator utilizing a novel time-domain bulk-driven offset cancellation scheme with minimal additional power consumption and delay. It uses an open loop dynamic phase detector to achieve very high precision. The circuit is designed in a 0.6-μm process. The simulation results show that the circuit consumes 540 nA current at 100 kHz clock frequency and the proposed offset cancellation scheme is able to reduce the input referred offset to within 25 μV from an initial value of 20 mV.