DocumentCode :
3019361
Title :
A simple analytic method for converting standardized IC-package thermal resistances (&thetas;ja, &thetas;jc) into a two-resistor model (&thetas;jb, &thetas;jt)
Author :
Tal, Yaniv ; Nabi, Aharon
Author_Institution :
Dept. R&D Eng., RAFAEL, Haifa, Israel
fYear :
2001
fDate :
2001
Firstpage :
134
Lastpage :
144
Abstract :
A typical data-sheets of an IC package supplied by a manufacturer, include two standardized thermal resistances, junction-to-ambient resistance θja and junction-to-case resistance θjc. It is well known that these two parameters are not applicable in thermal analysis of practical systems. Large errors can be encountered in predicting the die temperature. In recent years, the concept of “compact model” was introduced. It predicts die temperatures to a higher level of accuracy. The simplest is a two-resistor model with junction-to-board and junction-to-top as thermal resistors (θjb and θjt respectively). There are a number of methods for the creation of this model. Unfortunately, they requires information that is considered proprietary by the manufacturer. In this paper, we propose a novel approach that overcomes this difficulty. The two resistors are evaluated based solely on the manufacturer data-sheet. The method, named PERIMA, is a simple analytic algorithm, which is easy-to-use. The standard test methods for measuring the thermal resistances θja and θjc are analytically re-constructed and the unknown resistors θjb and θjt are derived. PERIMA was applied successfully for representative types of IC packages. The results compare very well with available data found in the literature, θjb with less than 20% and θjt in a range of 10% to 40%
Keywords :
error analysis; integrated circuit modelling; integrated circuit packaging; thermal analysis; thermal resistance; IC package; IC packages; PERIMA method; analytic algorithm; analytic method; data-sheets; die temperature; die temperature prediction errors; junction-to-ambient resistance; junction-to-board thermal resistor; junction-to-case resistance; junction-to-top thermal resistor; manufacturer data-sheet; proprietary data; standard test method reconstruction; standardized IC-package thermal resistance conversion; standardized thermal resistances; thermal analysis; thermal resistance; two-resistor model; Heat transfer; Integrated circuit modeling; Integrated circuit packaging; Manufacturing; Research and development; Resistors; Temperature; Testing; Thermal engineering; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal Measurement and Management, 2001. Seventeenth Annual IEEE Symposium
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6649-2
Type :
conf
DOI :
10.1109/STHERM.2001.915162
Filename :
915162
Link To Document :
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