Title :
Design techniques for HDTV switched-current decimators
Author :
Helfenstein, Markus ; Franca, José E. ; Moschytz, George S.
Author_Institution :
Inst. for Signal & Inf. Process., Swiss Federal Inst. of Technol., Zurich, Switzerland
Abstract :
The design of switched-current decimators for wide bandwidth video filtering applications is presented. Applying topologies with only one input commutator to switched-currents allows the design of high speed polyphase input branches with reduced distortion. These concepts were utilized in the implementation of a linear phase 19 tap FIR filter chip with an amplitude response tailored to video applications. It is expected that the prototype filter implemented in a 0.5 μm CMOS process will operate at an input sampling rate of 135 MHz and with a decimating factor of 5
Keywords :
CMOS analogue integrated circuits; FIR filters; analogue processing circuits; delay circuits; high definition television; integrated circuit design; switched current circuits; television equipment; video signal processing; 0.5 micron; 135 MHz; CMOS process; amplitude response; circuit topology; design; distortion; high speed polyphase input branch; input commutator; linear phase FIR filter; sampling rate; switched-current decimator; video filtering; CMOS process; Finite impulse response filter; Frequency; HDTV; Prototypes; Sampling methods; Signal design; Signal processing; Signal sampling; Video signal processing;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.539862
