Title :
Design of a multistage decimation-interpolation filter
Author_Institution :
Tektronix, Inc., Beaverton, OR
Abstract :
A 2 chip digital multi-rate FIR filter implemented in 2 micron CMOS performs 10 million multiplications and 20 million accumulations per second. The filter has 48 programmable bandwidths in a 1-2-5 sequence, and can either interpolate or decimate. This paper describes the design and implementation of the filter.
Keywords :
Band pass filters; Control systems; Convolution; Digital filters; Filtering; Finite impulse response filter; Frequency; Hardware; Interpolation; Passband;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.
DOI :
10.1109/ICASSP.1987.1169830
