Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAs

Author

Upegui, Andres ; Izui, J. ; Curchod, G.

Author_Institution

InIT Inst. - hepia, Univ. of Appl. Sci. of Western Switzerland, Geneva, Switzerland

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

1

Lastpage

6

Abstract

This paper presents a technique to mitigated SEU faults on Virtex-5 FPGAs through the use of dynamic partial reconfiguration. The key idea is to reconfigure the damaged part of the configuration bitstream in order to repair the bitstream and, thus, the overlying architecture. To this end, we propose a design flow and a set of tools that allow us to manipulate the bitstream generation. As case study, we present an application using an AES encryption coprocessor, a fault detection system constantly verifying system integrity and repairing faults, and an independent program injecting faults to validate the system.

Keywords

coprocessors; cryptography; fault diagnosis; fault tolerant computing; field programmable gate arrays; integrated circuit reliability; reconfigurable architectures; AES encryption coprocessor; SEU faults; Virtex-5 FPGA dynamic partial reconfiguration; bitstream generation; configuration bitstream; design flow; fault detection system; fault injection program; fault mitigation; fault repairing; overlying architecture; system integrity; Circuit faults; Computer architecture; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Registers; Routing; FPGA; dynamic partial reconfiguration; fault tolerance;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4673-2919-4

Type

conf

DOI

10.1109/ReConFig.2012.6416752

Filename

6416752