DocumentCode
3019755
Title
A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection
Author
Okada, Makoto ; Hiramatsu, Tatsuo ; Nakajima, Hiroshi ; Ozone, Makoto ; Hirase, Katsunori ; Kimura, Shinji
Author_Institution
Digital Syst. Dev. Center, Sanyo Electr. Co. Ltd., Osaka, Japan
fYear
2005
fDate
04-08 April 2005
Abstract
Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.
Keywords
C language; field programmable gate arrays; multi-threading; multiprocessor interconnection networks; parallel processing; reconfigurable architectures; video coding; ALU array architecture; C language; MPEG-4 video decoding application; dynamic reconfigurable processor; multithreading technology; parallel processing processor; source code; Clocks; Field programmable gate arrays; Flexible printed circuits; Hardware; Home appliances; Integrated circuit interconnections; Logic devices; Power system interconnection; Reconfigurable logic; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
Print_ISBN
0-7695-2312-9
Type
conf
DOI
10.1109/IPDPS.2005.64
Filename
1420005
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