A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory

This paper presents a new architecture for a coarse-grained reconfigurable array targeted to linear algebra problems. The reconfiguration memories are implemented using magnetic tunneling junctions. These storage elements provide for non-volatility and for a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional mesh of double precision floating-point execution units. The execution units are run-time reconfigurable. Its configuration information defines the operation to be executed and the data flow intra and inter execution units. The synthesis results of a prototype design of a 4×4 array targeting a 65 nm CMOS technology confirm that the proposed architecture is able to provide a very significant computational density and that the magnetic-based configuration memory can provide a very area efficient run-time reconfigurability.