Title :
A 10-bit 100 MSamples/s BiCMOS D/A converter
Author :
Jorgensen, Ivan Harald Holger ; Tunheim, Svein Anders
Author_Institution :
Electron. Inst., Tech. Univ. Lyngby, Denmark
Abstract :
A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR1) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the measured SFDR was approximately 43 dB
Keywords :
BiCMOS integrated circuits; digital-analogue conversion; direct digital synthesis; emitter-coupled logic; 0.8 micron; 10 bit; 100 MHz; 5 V; 650 mW; BiCMOS D/A converter; LSB; bipolar differential pair; current cell matrix; current-steering D/A converter; differential nonlinearity; direct digital synthesis; dynamic nonlinearities; emitter-coupled logic flip-flop; global ECL clock; integral nonlinearity; power consumption; spurious free dynamic range; BiCMOS integrated circuits; Clocks; Dynamic range; Energy consumption; Flip-flops; Frequency measurement; Frequency synthesizers; Logic; Process design; Semiconductor device measurement;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.539975