DocumentCode :
3020013
Title :
Memory efficient column-layered decoder design for non-binary LDPC codes
Author :
He, Kai ; Sha, Jin ; Wang, Zhongfeng
Author_Institution :
Sch. of Electron. Sci. & Eng., Nanjing Univ., Nanjing, China
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
2613
Lastpage :
2616
Abstract :
Low-density parity-check (LDPC) codes constructed over the Galois field GF(q) (q>;2), which are also called non-binary LDPC codes, are an extension of binary LDPC codes with significantly better performance. In this paper, an efficient column-layered decoding algorithm, which can reduce the message memory as well as the average number of iterations dramatically, is proposed for min-max decoding. In addition, a non-uniform quantization scheme is developed for reducing the word length while achieving similar performances compared to a conventional quantization scheme. Meanwhile, the corresponding decoder architecture is also proposed.
Keywords :
data reduction; decoding; parity check codes; quantisation (signal); Galois field; column-layered decoding algorithm; decoder architecture; low-density parity-check codes; memory efficient column-layered decoder design; message memory reduction; min-max decoding; nonbinary LDPC codes; nonuniform quantization scheme; Algorithm design and analysis; Decoding; Iterative decoding; Memory management; Quantization; Non-binary low-density parity-check (NB-LDPC) codes; column-layer; decoder architecture; min-max; non-uniform quantization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271841
Filename :
6271841
Link To Document :
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