Title :
I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os
Author :
Yasar, Gulsun ; Chiu, Charles ; Proctor, Robert A. ; Libous, James P.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs
Keywords :
VLSI; application specific integrated circuits; cellular arrays; circuit layout CAD; electromigration; integrated circuit layout; integrated circuit noise; integrated circuit reliability; I/O cell placement; IR drop; dI/dt noise issues; design process; electrical checking algorithms; electrical checking methodology; electromigration; high quality ASICs; peripheral I/Os; placement guidelines; power distribution network; Application specific integrated circuits; CMOS technology; Ceramics; Copper; Electromigration; Guidelines; Microelectronics; Packaging; Power supplies; Process design;
Conference_Titel :
Quality Electronic Design, 2001 International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1025-6
DOI :
10.1109/ISQED.2001.915208
